1. Field of the Invention
The invention relates in general to a method of forming a polycide gate, and more particularly, to a method of preventing the silicide layer to peel from the polycide gate.
2. Description of the Related Art
In the semiconductor fabrication process, the polycide gate formed of lightly doped polysilicon and tungsten silicide is commonly used for commercial. In FIG. 1, the cross setion view of a conventional polycide gate is shown. A gate oxide layer 102, a polysilicon layer 104 and a tungsten silicide layer 106 are formed on a substrate 100. Through photolithography and etching process, the polycide gate 108 is formed. A spacer 110 is formed on a side wall of the polycide gate 108. In the subsequent process, a dielectric layer 112 with on opening 114 exposing a part of the substrate 100 is formed over the substrate 100. The opening 114 is filled with conductive material to electrically connect with the substrate. As the dimension of semiconductor is developed to a line width of 0.25 .mu.m, the size of the opening 114 is concomitantly shrunk. As a consequently, being restricted by the resolution of the exposure stepper, the opening 114 cannot afford to be shrunk unlimitedly. Therefore, the fabrication process for forming the opening 114 as shown in FIG. 1 does not meet the requirements of the fabrication line.
A method of self-aligned contact (SAC) is developed for solving the problem of the fabrication process mentioned above. In FIG. 2, a gate oxide layer 202, a polysilicon layer 204, and a tungsten silicide layer 206 are formed on a substrate 200. A silicon nitride layer 208 is formed on the tungsten silicide layer 206. Using photolithography and etching process, a gate 210 is formed. A spacer 212 is formed on a side wall of the gate 210 and the silicon nitride layer 208. Similar to the above process, a dielectric layer 214 with an opening 216 exposing the spacer 212, a part of the substrate 200 and the silicon nitride layer 208 is formed over the substrate 200.
The formation of the spacer 212 and the silicon nitride layer 208 are functioned as a hard mask layer for the tungsten silicide layer 206 as well as the polycide gate 210. A larger selectivity of the dielectric layer to the silicon nitride layer 214 is chosen for the etching process of forming the opening 216. The etchant used for the etching process etches the dielectric layer 214 along the profile of the silicon nitride layer 208 and the spacer 212 to form the opening 216. Thus, the formation of the opening 216 is formed without the restriction of the resolution of the exposure stepper. The silicon nitride layer 208 is used as an etch stop layer for forming the opening 216. However, due to the different mechanical properties such as the different thermal expansion coefficient between the silicon nitride layer 208 and the tungsten silicide layer 206, the silicon nitride layer 208 is easy to peel from the tungsten silicide layer 206.
Moreover, to improve the conductivity of the tungsten silicide layer 206, the mass ratio of the tungsten to silicon (W/Si) has to be increased. The more the tungsten proportion is increased, the more the stress is between the tungsten silicide layer 206 and the silicon nitride layer 208 to cause the silicon nitride layer 208 to peel.